The present invention relates to a current comparison type latch for use in an analog-digital converter, and the like.
In the prior art, a voltage comparison type latch has been the mainstream latch for use in an analog-digital converter, and the like. However, as the recent trend toward reducing the voltage of an LSI, signal processing operations are now often performed by using a current, and there is an increasing demand for a current comparison type latch.
A conventional current comparison type latch is disclosed in an article xe2x80x9cA 100 MHz 8 BIT CMOS INTERPOLATING A/D CONVERTER, M. Steyaert, R. Roovers and J. Craninckxxe2x80x9d (IEEE 1993 CUSTOM INTEGRATED CIRCUITS CONFERENCE 28.1.1-28.1.4). As illustrated in FIG. 9, the current comparison type latch includes: input terminals IN1 and IN2 to which two signals to be compared are input, respectively; two output terminals OUT and OUTB; n-type transistors Q1 and Q2 whose gates are connected to a high potential side power supply VDD; an n-type transistor Q3 and a p-type transistor Q5 forming a first inverter, and an n-type transistor Q4 and a p-type transistor Q6 forming a second inverter, wherein the output of the first inverter is connected to the input of the second inverter and the output of the second inverter is connected to the input of the first inverter; and an n-type transistor Q7 provided between the input terminals of the two inverters for switching between a latch operation and a reset operation. In the current comparison type latch, the n-type transistor Q7 is turned ON, thereby performing a reset operation, when a control signal STB applied to the gate of the n-type transistor Q7 is at an xe2x80x9cHxe2x80x9d level, whereas the n-type transistor Q7 is turned OFF, thereby performing a latch operation, when the control signal STB is at an xe2x80x9cLxe2x80x9d level.
However, with the conventional current comparison type latch configuration, during a reset phase, the transistor Q7 is turned ON, whereby the gate potentials of the four transistors Q3 to Q6 forming the two inverters and the potentials of the two output terminals OUT and OUTB are all at the same potential. Therefore, the output potentials of the output terminals OUT and OUTB are not fixed at a logic level (the xe2x80x9cHxe2x80x9d level (the potential of the high potential side power supply VDD) or the xe2x80x9cLxe2x80x9d level (the potential of the low potential side power supply VSS)), but is fixed to a predetermined intermediate potential between these potentials. As a result, a through current flows from the high potential side power supply VDD to the low potential side power supply VSS via the transistors Q5, Q3 and Q1, and a through current also flows from the high potential side power supply VDD to the low potential side power supply VSS via the transistors Q6, Q4 and Q2, thereby increasing the power consumption during the reset phase.
Moreover, with the conventional current comparison type latch configuration, the output potential of each of the two output terminals OUT and OUTB being in a reset state is at the predetermined intermediate potential, as described above, and is not at a logic level (the xe2x80x9cHxe2x80x9d level or the xe2x80x9cLxe2x80x9d level). Therefore, in order to convert the output data of the current comparison type latch into one-clock-cycle data, a further stage of latch is required, thereby hindering a high-speed operation.
An object of the present invention is to provide a current comparison type latch which eliminates the through current flowing in a reset state so as to achieve a reduction in the power consumption, and which is capable of making a high-speed and high-precision comparison.
In order to achieve the above-described object, the present invention provides a current comparison type latch in which the output potential of an output terminal in a reset state can be fixed to a logic level (the xe2x80x9cHxe2x80x9d level or the xe2x80x9cLxe2x80x9d level).
Specifically, a current comparison type latch of the present invention includes: a first input terminal and a second input terminal to which two current signals to be compared with each other are input, respectively; a third input terminal to which a clock signal for switching between a reset operation and a latch operation is input; a first output terminal and a second output terminal for outputting signals resulting from a comparison between the two signals input to the first and second input terminals; an n-type first transistor and an n-type second transistor whose gates receive a predetermined voltage and whose drains are connected to the first and second input terminals, respectively; an n-type third transistor and an n-type fourth transistor whose sources are connected to the drains of the first and second transistors, respectively; an n-type fifth transistor and an n-type sixth transistor whose sources are connected to drains of the third and fourth transistors, respectively; a p-type seventh transistor and a p-type eighth transistor whose drains are connected to drains of the fifth and sixth transistors, respectively; a p-type ninth transistor whose gate is connected to a gate of the third transistor and to the drain of the sixth transistor and whose drain is connected to the drain of the fifth transistor; a p-type tenth transistor whose gate is connected to a gate of the fourth transistor and to the drain of the fifth transistor and whose drain is connected to the drain of the sixth transistor; an n-type eleventh transistor whose gate is connected to the gate of the third transistor and whose drain is connected to the gate of the fourth transistor; an n-type twelfth transistor whose gate is connected to the gate of the fourth transistor and whose drain is connected to the gate of the third transistor; and an n-type thirteenth transistor whose drain is connected to sources of the eleventh and twelfth transistors, wherein: sources of the seventh, eighth, ninth and tenth transistors are connected to a high potential power supply line; sources of the first, second and thirteenth transistors are connected to a low potential power supply line; the third input terminal is connected to gates of the fifth, sixth, seventh, eighth and thirteenth transistors; and the first and second output terminals are connected to the drains of the seventh and eighth transistors.
In one embodiment, the current comparison type latch of the present invention further includes: a third output terminal and a fourth output terminal; a p-type fourteenth transistor whose gate is connected to the first output terminal; a p-type fifteenth transistor whose gate is connected to the second output terminal; an n-type sixteenth transistor whose drain is connected to a drain of the fourteenth transistor and whose gate is connected to a drain of the fifteenth transistor; and an n-type seventeenth transistor whose drain is connected to the drain of the fifteenth transistor and whose gate is connected to the drain of the fourteenth transistor, wherein: sources of the fourteenth and fifteenth transistors are connected to the high potential power supply line; sources of the sixteenth and seventeenth transistors are connected to the low potential power supply line; the third and fourth output terminals are connected to the drains of the fourteenth and fifteenth transistors; and the comparison result signals output from the first and second output terminals are converted into comparison result signals whose cycle is equal to one cycle of the clock signal so as to output the converted comparison result signals from the third and fourth output terminals, respectively.
In one embodiment, the current comparison type latch of the present invention further includes: a p-type eighteenth transistor whose drain and source are connected to the drain and the source of the fourteenth transistor and whose gate is connected to the drain of the fifteenth transistor; and a p-type nineteenth transistor whose drain and source are connected to the drain and the source of the fifteenth transistor and whose gate is connected to the drain of the fourteenth transistor.
In one embodiment, the current comparison type latch of the present invention further includes: a fourth input terminal and a fifth input terminal to which two voltage signals to be compared with each other are input, respectively; a current source; a p-type twentieth transistor whose drain is connected to the first input terminal and whose source is connected to the current source; and a p-type twenty-first transistor whose drain is connected to the second input terminal and whose source is connected to the current source, wherein: the fourth and fifth input terminals are connected to gates of the twentieth and twenty-first transistors, respectively; and the voltage signals input to the fourth and fifth input terminals are converted into current signals to be input to the first and second input terminals, respectively.
Alternatively, the polarities of the transistors described above may be changed so that each p-type transistor is replaced with an n-type transistor and each n-type transistor replaced with a p-type transistor. In such a case, the high potential power supply line is replaced with a low potential power supply line and the low potential power supply line is replaced with a high potential power supply line.
Thus, in the current comparison type latch of the present invention, the potential during a reset mode is fixed at a logic level (the xe2x80x9cHxe2x80x9d level or the xe2x80x9cLxe2x80x9d level), thereby eliminating the through current during a reset mode and thus achieving a reduction in the power consumption.
Moreover, by fixing the potential during a reset mode at a logic level (the xe2x80x9cHxe2x80x9d level or the xe2x80x9cLxe2x80x9d level), it is possible to latch and hold data without adding a further stage of a current comparison type latch of the same configuration, and to easily convert the data into data whose cycle is equal to one cycle of a clock signal. Therefore, it is possible to realize a high-speed and high-precision latch operation.